The present application is directed to an improved three-dimensional CMOS (complementary metal-oxide semiconductor) integrated circuit structure usable in VLSI (very large scale integration).
In the prior art such as Pashley U.S. Pat. No. 4,272,880, dated June 16, 1981, there has been shown multilayer integrated CMOS structures and processes in which complementary transistors, that is an n-channel and a p-channel field effect transistor are fabricated in vertical alignment with one another. A limitation of the structure of Pashley is that the upper CMOS transistor is an overlying polysilicon layer. Laser annealing is suggested to provide large crystals of silicone in the polysilicon layer, however, the device still has the inherent disadvantages of a polysilicon device.
In the present invention the localized overgrowth of epitaxial single crystal silicon over gate oxide is generally shown in FIG. 1 in which a single unitary crystal silicon substrate 10 has a field oxide dielectric layer 11 over it, preferably of silicon dioxide. A window or via 12 in the oxide layer 11 provides a starting point for selective epitaxial silicon overgrowth over short distances on the oxide surface near the window regions. In FIG. 1 this epitaxial lateral overgrowth is shown as beginning from the silicon surface 13, the epitaxial layer 14 having both vertical growth and lateral overgrowth 15. The lower part 10 and the upper part 14, 15 share a common crystalline lattice structure and form a single unitary crystalline structure. Typical growth conditions are laid out in FIG. 2 which shows certain parameters in a low pressure epitaxial reactor. The localized overgrowth (LOG) of silicon process in an epitaxial reactor is at reduced pressure and at relatively low temperature such as 40 torr and 950.degree. C., respectively, using the SiCl.sub.2 H.sub.2 /HCl/H.sub.2 system. The low pressure ensures low background doping and low particle contaminations and enables growth of the high quality crystal using SiH.sub.2 Cl.sub.2 /H.sub.2 system. The relatively low temperature of 950.degree. C. was selected to minimize the source-drain doping impurity redistribution in the lower transistor. This is in contrast to recrystallization which involves melting at near 1430.degree. C. Growth conditions to give a good quality overgrowth layer have been discussed for the SiH.sub.2 Cl.sub.2 /H.sub.2 reactant gases by introducing the HCl gas. Furthermore, the use of HCl ensures clean surfaces for LOG and have low oxide charge density. The use of HCl gas has been shown to suppress polysilicon nuclei formation on SiO.sub.2.
In this invention an improved three-dimensional CMOS structure and process is described based on the localized overgrowth of high-quality thin-film silicon over gate oxide for a distance of the order of a channel length, i.e., on the order of a micron or two. This provides a methodology for very high density and high performance three-dimensional (3D) logic circuits.